Nonvolatile memory device having a ferroelectric layer

ABSTRACT

A nonvolatile memory device according to an embodiment includes a substrate having an upper surface, and a gate structure disposed over the substrate. The gate structure includes at least one gate electrode layer pattern and at least one gate insulation layer pattern, which are alternately stacked along a first direction perpendicular to the upper surface. The gate structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes a ferroelectric layer disposed on at least a portion of one sidewall surface of the gate structure. The one sidewall surface of the gate structure forms a plane substantially parallel to the first and second directions. The nonvolatile memory device includes a channel layer disposed on the ferroelectric layer, and a source electrode structure and a drain electrode structure disposed to contact the channel layer and spaced apart from each other in the second direction.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) toKorean Patent Application No. 10-2019-0163139, filed on Dec. 9, 2019,which is herein incorporated by reference in its entirety.

BACKGROUND 1. Technical Field

The present disclosure relates generally to a nonvolatile memory deviceand, more particularly, to a nonvolatile memory device having aferroelectric layer.

2. Related Art

As the design rule decreases and the degree of integration increases,research has continued on the structures of semiconductor devices thatcan guarantee both structural stability and reliability of signalstorage operations. Currently, a flash memory device with a chargestorage scheme using a three-layer stacked structure of a chargetunneling layer, a charge trap layer, and a charge barrier layer hasbeen widely utilized.

Recently, various nonvolatile memory devices having different structuresfrom existing flash memory devices have been proposed. An example of anonvolatile memory device is a ferroelectric memory device of atransistor structure. The ferroelectric memory device can non-volatilelystore any one of remanent polarization having different sizes andorientations as signal information in a gate ferroelectric layer. Inaddition, the signal information may be read out by using a feature inwhich the magnitude of the operation current flowing through a channellayer between source and drain electrodes changes according to thestored remanent polarization.

SUMMARY

A nonvolatile memory device according to an aspect of the presentdisclosure includes a substrate having an upper surface, and a gatestructure disposed over the substrate. The gate structure includes atleast one gate electrode layer pattern and at least one gate insulationlayer pattern, which are alternately stacked along a first directionperpendicular to the upper surface. The gate structure extends in asecond direction perpendicular to the first direction. In addition, thenonvolatile memory device includes a ferroelectric layer disposed on atleast a portion of one sidewall surface of the gate structure over thesubstrate. The one sidewall surface of the gate structure is a planedefined by the first and second directions. The nonvolatile memorydevice includes a channel layer disposed over the substrate and disposedon the ferroelectric layer, and a source electrode structure and a drainelectrode structure each disposed over the substrate and disposed tocontact the channel layer. The source electrode structure and the drainelectrode structure are spaced apart from each other in the seconddirection.

A nonvolatile memory device according to another aspect of the presentdisclosure includes a substrate having an upper surface, and a gatestructure disposed over the substrate. The gate structure includes atleast one gate electrode layer pattern and at least one gate insulationlayer pattern, which are alternately stacked along a first directionperpendicular to the upper surface. The gate structure extends in asecond direction perpendicular to the first direction. The nonvolatilememory device includes a ferroelectric layer disposed on at least aportion of one sidewall surface of the gate structure, over thesubstrate. The one sidewall surface of the gate structure forms a planesubstantially parallel to the first and second directions. Thenonvolatile memory device includes a source electrode structure and adrain electrode structure disposed on the ferroelectric layer spacedapart from each other in the second direction, and a channel structuredisposed over the substrate and disposed between the source electrodestructure and the drain electrode structure. Each of the sourceelectrode structure and the drain electrode structure is disposed on theferroelectric layer.

A nonvolatile memory device according to another aspect of the presentdisclosure includes a substrate, and a gate structure disposed over thesubstrate having an upper surface. The gate structure includes at leastone gate functional layer pattern and at least one gate insulation layerpattern, which are alternately stacked along a first directionperpendicular to the upper surface. The gate structure extends in asecond direction perpendicular to the first direction. The nonvolatilememory device includes an interfacial insulation layer and a channellayer, which are sequentially disposed on one sidewall surface of thegate structure. The one sidewall surface of the gate structure is aplane defined by the first and second directions. The nonvolatile memorydevice includes a source electrode structure and a drain electrodestructure spaced apart from each other in the second direction. Each ofthe source electrode structure and the drain electrode structurecontacts the channel layer. The gate functional layer pattern includes afloating electrode layer part disposed on the interfacial insulationlayer and the gate insulation layer pattern, a ferroelectric layer partdisposed on the floating electrode layer part, and the interfacialinsulation layer, and a gate electrode layer part disposed to contactthe ferroelectric layer part.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective view schematically illustrating a nonvolatilememory device according to an embodiment of the present disclosure.

FIG. 2 is a plan view of the nonvolatile memory device of FIG. 1.

FIG. 3 is a cross-sectional view taken along a line A-A′ of thenonvolatile memory device of FIG. 1.

FIGS. 4A to 4E are views schematically illustrating an operation of anonvolatile memory device according to an embodiment of the presentdisclosure.

FIG. 5 is a perspective view schematically illustrating a nonvolatilememory device according to another embodiment of the present disclosure.

FIG. 6A is a circuit diagram schematically illustrating the nonvolatilememory device of FIG. 5.

FIG. 6B is a partial plan view of the nonvolatile memory devicecorresponding to the circuit of FIG. 6A.

FIG. 6C is a cross-sectional view taken along a line C-C′ of FIG. 6B.

FIG. 7 is a perspective view schematically illustrating a nonvolatilememory device according to another embodiment of the present disclosure.

FIG. 8 is a plan view of the nonvolatile memory device of FIG. 7.

FIG. 9 is a cross-sectional view taken along a line D-D′ of thenonvolatile memory device of FIG. 7.

FIG. 10 is a perspective view schematically illustrating a nonvolatilememory device according to yet another embodiment of the presentdisclosure.

FIG. 11 is a plan view of the nonvolatile memory device of FIG. 10.

FIG. 12 is a cross-sectional view taken along a line E-E′ of thenonvolatile memory device of FIG. 10.

FIG. 13 is a perspective view schematically illustrating a nonvolatilememory device according to still yet another embodiment of the presentdisclosure.

FIG. 14 is a plan view of the nonvolatile memory device of FIG. 13.

FIG. 15 is a cross-sectional view taken along a line F-F′ of thenonvolatile memory device of FIG. 13.

FIG. 16 is a perspective view schematically illustrating a nonvolatilememory device according to still yet another embodiment of the presentdisclosure.

FIG. 17 is a plan view of the nonvolatile memory device of FIG. 16.

FIG. 18 is a cross-sectional view taken along a line G-G′ of thenonvolatile memory device of FIG. 16.

FIG. 19 is a perspective view schematically illustrating a nonvolatilememory device according to a further embodiment of the presentdisclosure.

FIG. 20 is a plan view of the nonvolatile memory device of FIG. 19.

FIG. 21 is a cross-sectional view taken along a line H-H′ of thenonvolatile memory device of FIG. 19.

FIG. 22 is a perspective view schematically illustrating a nonvolatilememory device according to a still further embodiment of the presentdisclosure.

FIG. 23 is a plan view of the nonvolatile memory device of FIG. 22.

FIG. 24 is a cross-sectional view taken along a line I-I′ of thenonvolatile memory device of FIG. 22.

DETAILED DESCRIPTION

Hereinafter, embodiments of the present disclosure will be described indetail with reference to the accompanying drawings. In the drawings, inorder to clearly express the components of each device, the sizes of thecomponents, such as width and thickness of the components, are enlarged.The terms used herein may correspond to words selected in considerationof their functions in the embodiments, and the meanings of the terms maybe construed to be different according to the ordinary skill in the artto which the embodiments belong. If expressly defined in detail, theterms may be construed according to the definitions. Unless otherwisedefined, the terms (including technical and scientific terms) usedherein have the same meaning as commonly understood by one of ordinaryskill in the art to which the embodiments belong.

In addition, expression of a singular form of a word should beunderstood to include the plural forms of the word unless clearly usedotherwise in the context. It will be understood that the terms“comprise” or “have” are intended to specify the presence of a feature,a number, a step, an operation, a component, an element, a part, orcombinations thereof, but not used to preclude the presence orpossibility of addition one or more other features, numbers, steps,operations, components, elements, parts, or combinations thereof.

In this specification, the term “a predetermined direction” may mean adirection encompassing one direction determined in a coordinate systemand a direction opposite to the one direction. As an example, in thex-y-z coordinate system, the z-direction may mean all of a direction inwhich an absolute value of the z-axis increases in a positive directionalong the z-axis from the origin 0 and a direction in which an absolutevalue of the z-axis increases in a negative direction along the z-axisfrom the origin 0. The x-direction and the y-direction may each beinterpreted in substantially the same way in the x-y-z coordinatesystem.

FIG. 1 is a perspective view schematically illustrating a nonvolatilememory device 1 according to an embodiment of the present disclosure.FIG. 2 is a plan view of the nonvolatile memory device of FIG. 1. FIG. 3is a cross-sectional view taken along a line A-A′ of the nonvolatilememory device of FIG. 1.

Referring to FIGS. 1 to 3, the nonvolatile memory device 1 may include asubstrate 101, first and second gate structures 12 and 14, a sourceelectrode structure 22, a drain electrode structure 24, first and secondferroelectric layers 312 and 314, and first and second channel layers322 and 324. In addition, the nonvolatile memory device 1 may furtherinclude a base insulation layer 110 disposed on the substrate 101 and aninsulation structure 26 extending in a first direction (i.e., thez-direction) perpendicular to the substrate 101. A memory devicestructure including the first gate structure 12, the first ferroelectriclayer 312 and the first channel layer 322 may share the source electrodestructure 22, the drain electrode structure 24 and the insulationstructure 26 with a memory device structure including the second gatestructure 14, the second ferroelectric layer 314 and the second channellayer 324.

The substrate 101 may include a semiconductor material. Specifically,the semiconductor material may include silicon (Si), germanium (Ge),gallium arsenide (GaAs), and the like. The substrate 101 may be dopedwith an n-type dopant or a p-type dopant. As an example, the substrate101 may include a well region doped with an n-type dopant or a p-typedopant.

The base insulation layer 110 may be disposed on the substrate 101. Thebase insulation layer 110 may electrically insulate the first and secondgate structures 12 and 14, the first and second ferroelectric layers 312and 314, the first and second channel layers 322 and 324, the sourceelectrode structure 22, and the drain electrode structure 24 from thesubstrate 101, respectively.

Although not illustrated in FIG. 1, at least one conductive layer and atleast one insulation layer may be disposed between the substrate 101 andthe base insulation layer 110. The conductive layer and the insulationlayer may form various circuit patterns. That is, the conductive layerand the insulation layer may form a plurality of wirings or mayconstitute a passive element such as a capacitor or a resistor, or anactive element such as a diode or a transistor, by way of non-limitingexamples.

Referring to FIG. 1, the first gate electrode structure 12 may bedisposed on the base insulation layer 110. The first gate electrodestructure 12 may include first to fourth gate electrode layer patterns122 a, 122 b, 122 c and 122 d and first to fifth gate insulation layerpatterns 132 a, 132 b, 132 c, 132 d and 132 e, which are alternatelystacked along the first direction (i.e., the z-direction) perpendicularto the substrate 101, on the base insulation layer 110. The first gateinsulation layer pattern 132 a may be disposed to contact the baseinsulation layer 110. The fifth gate insulation layer pattern 132 e maybe disposed as an uppermost layer of the first gate electrode structure12.

The first gate electrode structure 12 may extend in a second direction(i.e., the y-direction) perpendicular to the first direction. The firstto fourth gate electrode layer patterns 122 a, 122 b, 122 c and 122 dmay be electrically insulated from each other by the first to fifth gateinsulation layer patterns 132 a, 132 b, 132 c, 132 d and 132 e. Thefirst to fourth gate electrode layer patterns 122 a, 122 b, 122 c and122 d may be conductive lines extending in the second direction (i.e.,the y-direction). The first to fourth gate electrode layer patterns 122a, 122 b, 122 c and 122 d may each maintain a predetermined potential.

In an embodiment, the first to fourth gate electrode layer patterns 122a, 122 b, 122 c and 122 d may each include a conductive material. Theconductive material may, for example, include a doped semiconductormaterial, metal, conductive metal silicide, conductive metal nitride, orconductive metal oxide. The conductive material may, for example,include n-type doped silicon, tungsten (W), titanium (Ti), copper (Cu),aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridiumoxide, tungsten nitride, titanium nitride, tantalum nitride, tungstencarbide, titanium carbide, tungsten silicide, titanium silicide,tantalum silicide, ruthenium oxide, or a combination of two or morethereof. The first to fifth gate insulation layer patterns 132 a, 132 b,132 c, 132 d and 132 e may each include an insulative material. Theinsulative material may, for example, include oxide, nitride,oxynitride, and the like.

In some other embodiments, the number of the gate electrode layerpatterns of the first gate electrode structure 12 may not necessarily belimited to four. The gate electrode layer patterns may be disposed indifferent various numbers, and the gate insulation layer patterns mayinsulate the various numbers of source electrode layer patterns alongthe first direction (i.e., the z-direction).

Referring to FIGS. 1 to 3, the first ferroelectric layer 312 may bedisposed on the base insulation layer 110 and on one sidewall surface S1of the first gate structure 12. Here, the one sidewall surface S1 mayform a plane substantially parallel to the first and second directions(i.e., a y-z plane to the z-direction and y-direction). The firstferroelectric layer 312 may have a predetermined thickness t1 along athird direction (i.e., the x-direction) perpendicular to the first andsecond directions. The thickness t1 may, for example, be 1 nanometers(nm) to 50 nanometers (nm), inclusive.

The first ferroelectric layer 312 may include a ferroelectric material.The ferroelectric material may have electrical remanent polarization ina state where no external electric field is applied. In addition, in theferroelectric material, when an external electric field is applied, theelectrical polarization may exhibit a hysteresis behavior. Bycontrolling the external electric field, one of a plurality of stablepolarization states on the polarization hysteresis curve can be writtenin the ferroelectric material. After the external electric field isremoved from the ferroelectric material, the written polarization can bestored in the ferroelectric material in a form of remanent polarization.The remanent polarization may be used in nonvolatile storage for aplurality of pieces of signal information. The first ferroelectric layer312 may, for example, include hafnium oxide, zirconium oxide, hafniumzirconium oxide, and the like. The first ferroelectric layer 312 mayhave a crystal structure of an orthorhombic system.

The first channel layer 322 may be disposed on the base insulation layer110 and contact the first ferroelectric layer 312. Specifically, thefirst channel layer 322 may be disposed on one surface S2 of the firstferroelectric layer 312 defined by the first and second directions(i.e., the z-direction and y-direction). The first channel layer 322 mayhave a predetermined thickness t2 along the third direction (i.e., thex-direction). The thickness t2 may, for example, be 1 nanometers (nm) to50 nanometers (nm), inclusive. Although the thickness of the firstferroelectric layer 312 is illustrated to be greater than the thicknessof the first channel layer 322 in FIG. 3, the thickness of the firstferroelectric layer 312 is not limited thereto, and in other embodimentsthe thickness of the first ferroelectric layer 312 may be less than orequal to the thickness of the first channel layer 322.

The first channel layer 322 may provide a path through which electricalcarriers such as electrons or holes move between the source electrodestructure 22 and the drain electrode structure 24. The electricalresistance of the first channel layer 322 may be reduced when aconductive channel is formed in the first channel layer 322, asdescribed later. However, the electrical resistance of the conductivechannel may also vary depending on the size and direction of theremanent polarization stored in the first ferroelectric layer 312.

The first channel layer 322 may include, for example, a dopedsemiconductor material or metal oxide. The semiconductor material may,for example, include silicon (Si), germanium (Ge), gallium arsenide(GaAs), and the like. The metal oxide may include indium-gallium-zinc(In—Ga—Zn) oxide. In an embodiment, the first channel layer 322 mayinclude silicon (Si) doped with an n-type dopant. Alternatively, thefirst channel layer 322 may include c-axis aligned indium-gallium-zinc(In—Ga—Zn) oxide. The first channel layer 322 may have a single crystalstructure or a polycrystalline structure.

Referring to FIGS. 1 to 3 again, the source electrode structure 22 andthe drain electrode structure 24 may each be disposed on the baseinsulation layer 110 to contact surface S3 of the first channel layer322, while being spaced apart from each other in the second direction(i.e., the y-direction). The source electrode structure 22 and the drainelectrode structure 24 may each have a pillar-like shape extending alongthe first direction (i.e., the z-direction). The source electrodestructure 22 and the drain electrode structure 24 may each be disposedto contact the first channel layer 322 and the second channel layer 324.

The insulation structure 26 may be disposed between the source electrodestructure 22 and the drain electrode structure 24. The insulationstructure 26 may be disposed to contact the first channel layer 322 andthe second channel layer 324. The insulation structure 26 may have apillar-like shape extending in the first direction (i.e., z-direction)from the base insulation layer 110. The insulation structure 26 may playa role in inhibiting the movement of the electrical carriers between thesource electrode structure 22 and the drain electrode structure 24through paths other than the first channel layer 322 or the secondchannel layer 324.

The source electrode structure 22 and the drain electrode structure 24may each maintain a predetermined electric potential. The electricpotential of each of the source electrode structure 22 and the drainelectrode structure 24 may be the same or different from each other. Inan embodiment, during an operation of the nonvolatile memory device, ifa conductive channel is formed in the first channel layer 322 or thesecond channel layer 324 and a predetermined potential difference occursbetween the source electrode structure 22 and the drain electrodestructure 24, the electrical carriers may move through the conductivechannel.

The source electrode structure 22 and the drain electrode structure 24may each include a conductive material. The conductive material may, forexample, include a doped semiconductor material, metal, conductive metalnitride, conductive metal oxide, conductive metal carbide, conductivemetal silicide, and the like. The conductive material may, for example,include doped silicon, tungsten (W), titanium (Ti), copper (Cu),aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridiumoxide, tungsten nitride, titanium nitride, tantalum nitride, tungstencarbide, titanium carbide, tungsten silicide, titanium silicide,tantalum silicide, ruthenium oxide, or a combination of two or morethereof. The insulation structure 26 may include oxide, nitride, oroxynitride. As an example, the insulation structure 26 may includesilicon oxide, silicon nitride, or silicon oxynitride.

Referring to FIGS. 1 to 3, the second channel layer 324 may be disposedon the base insulation layer 110 and may contact sidewalls of the sourceelectrode structure 22, drain electrode structure 24 and insulationstructure 26. Sidewalls of the source electrode structure 22, drainelectrode structure 24 and insulation structure 26 may be positioned onthe same plane S4. The plane S4 may form a plane substantially parallelto the first and second directions (i.e., a y-z plane parallel to thez-direction and y-direction). The second channel layer 324 may have apredetermined thickness t2 along the third direction (i.e., thex-direction). The configuration of the second channel layer 324 may besubstantially the same as the configuration of the first channel layer322.

The second ferroelectric layer 314 may be disposed on the baseinsulation layer 110 and on one surface S5 of the second channel layer324. The one surface S5 may be a plane defined by the first and seconddirections (i.e., a y-z plane parallel to the z-direction andy-direction). The second ferroelectric layer 314 may have apredetermined thickness t1 along the third direction (i.e., thex-direction). The configuration of the second ferroelectric layer 314may be substantially the same as the configuration of the firstferroelectric layer 312.

The second gate structure 14 may be disposed on the base insulationlayer 110 and contact one surface S6 of the second ferroelectric layer314. The plane S6 may form a plane substantially parallel to the firstand second directions (i.e., a y-z plane parallel to the z-direction andy-direction). The second gate structure 14 may include first to fourthgate electrode layer patterns 124 a, 124 b, 124 c and 124 d and first tofifth gate insulation layer patterns 134 a, 134 b, 134 c, 134 d and 134e, which are alternately stacked along the first direction (i.e., thez-direction). The first gate insulation layer pattern 134 a may bedisposed to contact the base insulation layer 110. The fifth gateinsulation layer pattern 134 e may be disposed as the uppermost layer ofthe second gate structure 14. The second gate structure 14 may extend inthe second direction (i.e., the y-direction). The configurations of thefirst to fourth gate electrode layer patterns 124 a, 124 b, 124 c and124 d and the first to fifth gate insulation layer patterns 134 a, 134b, 134 c, 134 d and 134 e of the second gate structure 14 may besubstantially the same as the configurations of the first to fourth gateelectrode layer patterns 122 a, 122 b, 122 c and 122 d and the first tofifth gate insulation layer patterns 132 a, 132 b, 132 c, 132 d and 132e of the first gate structure 12.

As described above, in the nonvolatile memory device 1 according to anembodiment of the present disclosure, the first gate structure 12 andthe second gate structure 14 may be disposed symmetrically with respectto each other across a y-z plane centered on the source electrodestructure 22, the insulation structure 26, and the drain electrodestructure 24. Similarly, the first ferroelectric layer 312 and thesecond ferroelectric layer 314 may be disposed symmetrically withrespect to each other, and the first channel layer 322 and the secondchannel layer 324 may be disposed symmetrically with respect to eachother.

In an embodiment, the first gate structure 12, the first ferroelectriclayer 312, the first channel layer 322, the source electrode structure22 and the drain electrode structure 24 may constitute one operationunit of the nonvolatile memory device 1, and the second gate structure14, the second ferroelectric layer 314, the second channel layer 324,the source electrode structure 22 and the drain electrode structure 24may constitute another operation unit of the nonvolatile memory device1. The source electrode structure 22 and the drain electrode structure24 may be shared by the different operation units. That is, the first tofourth gate electrode layer patterns 122 a, 122 b, 122 c and 122 d ofthe first gate structure 12, the first ferroelectric layer 312 and thefirst channel layer 322 may operate together with the source electrodestructure 22 and the drain electrode structure 24. In addition, thefirst to fourth gate electrode layer patterns 124 a, 124 b, 124 c and124 d of the second gate structure 14, the second ferroelectric layer314 and the second channel layer 324 may operate together with thesource electrode structure 22 and the drain electrode structure 24.

FIGS. 4A to 4E are views schematically illustrating an operation of anonvolatile memory device according to an embodiment of the presentdisclosure. FIG. 4A is a circuit diagram of a nonvolatile memory deviceaccording to an embodiment of the present disclosure. FIG. 4B is a planview of a portion of the nonvolatile memory device corresponding to thecircuit diagram of FIG. 4A. FIGS. 4C and 4D are views schematicallyillustrating different remanent polarization stored in a ferroelectriclayer of a nonvolatile memory device according to an embodiment of thepresent disclosure. FIG. 4E is a cross-sectional view taken along a lineB-B′ of FIG. 4B.

Specifically, FIG. 4B is a plan view schematically illustrating oneoperation unit 1 a of the nonvolatile memory device 1 described abovewith reference to FIGS. 1 to 3. The one operation unit 1 a may, forexample, include a first gate structure 12, a first ferroelectric layer312, a first channel layer 322, a source electrode structure 22, a drainelectrode structure 24 and an insulation structure 26. For theconvenience of explanation related to the operation of the one operationunit 1 a, the uppermost gate insulation layer pattern 134 e of the firstgate structure 12 is omitted in FIG. 4B.

Referring to FIG. 4A, first to fourth memory cells MC1, MC2, MC3 and MC4are disclosed. The first to fourth memory cells MC1, MC2, MC3 and MC4may each have a form of a transistor and include first to fourthferroelectric layers FD1, FD2, FD3 and FD4 functioning as memory layers,respectively.

A source and a drain of each of the first to fourth memory cells MC1,MC2, MC3 and MC4 may be electrically connected to a global source line(GSL) and a global drain line (GDL). Gate electrodes of the first tofourth memory cells MC1, MC2, MC3 and MC4 may be electrically connectedto first to fourth word lines GL1, GL2, GL3 and GL4, respectively.

In relation to a write operation for at least one memory cell of thefirst to fourth memory cells MC1, MC2, MC3 and MC4, first, at least oneof the first to fourth word lines GL1, GL2, GL3 and GL4 may be selected.A polarization switching voltage having a magnitude greater than orequal to a predetermined threshold voltage may be applied to both endsof each of the first to fourth ferroelectric layers FD1, FD2, FD3 andFD4 of the corresponding first to fourth memory cells MC1, MC2, MC3 andMC4, through the at least one selected word line. At this time, theglobal source line GSL and the global drain line GDL may be grounded. Byapplying a polarization switching voltage, the polarization of the firstto fourth ferroelectric layers FD1, FD2, FD3 and FD4 may be switched andthen aligned in a predetermined direction. After the polarizationswitching voltage is removed, the switched polarization may be stored inthe corresponding first to fourth ferroelectric layers FD1, FD2, FD3 andFD4 in the form of remanent polarization. As a result, as describedabove, the polarization switching voltage is applied through at leastone word line of the first to fourth word lines GL1, GL2, GL3 and GL4,so that a write operation may be performed on at least one of the firstto fourth memory cells MC1, MC2, MC3 and MC4. After the write operationis completed, a predetermined signal may be stored in the correspondingmemory cell in a nonvolatile manner.

Meanwhile, an operation of reading the signal non-volatilely stored inthe first to fourth memory cells MC1, MC2, MC3 and MC4 may be performed.As an exemplary example, a process of reading a signal stored in thefourth memory cell MC4 will be described. First, the fourth word lineGL4 corresponding to the fourth memory cell MC4 is selected.Subsequently, a read voltage greater than or equal to a predeterminedthreshold voltage may be applied to a gate electrode of the fourthmemory cell MC4 through the fourth word line GL4. An absolute value ofthe read voltage may be smaller than an absolute value of thepolarization switching voltage. That is, the polarization inside thefourth ferroelectric layer FD4 may not be switched by the read voltage.The transistor of the fourth memory cell MC4 is tuned on by the readvoltage, and a conductive channel may be formed in the channel layer ofthe transistor. As a result, when a source-drain potential difference isformed between the global source line GSL and the global drain line GDL,a source-drain current may flow through the conductive channel.

The source-drain current may vary according to the orientation and sizeof the remanent polarization stored in the fourth ferroelectric layerFD4. As an example, when the remanent polarization is oriented from thegate electrode toward the channel layer (corresponding to a firstpolarization DP1 in FIG. 4C), positive charges are accumulated insidethe fourth ferroelectric layer FD4 adjacent to the channel layer,thereby increasing the electron density of the conductive channel.Accordingly, the magnitude of the current flowing along the conductivechannel may be increased. As another example, when the remanentpolarization is oriented from the channel layer toward the gateelectrode (corresponding to a second polarization DP2 in FIG. 4D),negative charges are accumulated inside the fourth ferroelectric layerFD4 adjacent to the channel layer, thereby reducing the electron densityof the conductive channel. Accordingly, the magnitude of the currentflowing along the conductive channel may be reduced. As described above,the signal stored in the memory cell can be read by turning on thetransistor of the memory cell to be read and measuring the currentflowing through the channel layer.

In other embodiments, the number of the memory cells disposed betweenthe global source line GSL and the global drain line GDL is notnecessarily limited to four, and other various numbers are possible.Similarly, the number of the word lines is not necessarily limited tofour, and various other numbers are possible.

Referring to FIG. 4B, the global source line GSL described above withreference to FIG. 4A may correspond to the source electrode structure22, and the global drain line GDL may correspond to the drain electrodestructure 24. Also, the first to fourth word lines GLS, GL2, GL3 and GL4may correspond to the first to fourth gate electrode layer patterns 122a, 122 b, 122 c and 122 d of the first gate structure 12 in FIGS. 1-3.Accordingly, the fourth word line GL4 and the fourth ferroelectric layerFD4 of the fourth memory cell MC4 illustrated in FIG. 4A may correspondto the fourth gate electrode layer pattern 122 d and a region of thefirst ferroelectric layer 312 covered by the fourth gate electrode layerpattern 122 d illustrated in FIG. 4B. Referring to FIGS. 4B and 4E, achannel layer of the fourth memory cell MC4 illustrated in FIG. 4A maycorrespond to an eight region 322-h of the first channel layer 322,between source electrode structure 22 and drain electrode structure 24,covered by the fourth gate electrode layer pattern 122 d. Referring toFIGS. 1 to 3 and FIG. 4E, the first channel layer 322 may include firstto ninth regions 322-a, 322-b, 322-c, 322-d, 322-e, 322-f, 322-g, 322-hand 322-i that correspond to regions overlapping, between sourceelectrode structure 22 and drain electrode structure 24, the first tofourth gate electrode layer patterns 122 a, 122 b, 122 c and 122 d andthe first to fifth gate insulation layer patterns 132 a, 132 b, 132 c,132 d and 132 e along the third direction (i.e., the x-direction). As anexample, the channel layers of the first to third memory cells MC1, MC2and MC3 illustrated in FIG. 4A may correspond to the second region322-b, the fourth region 322-d and the sixth region 322-f of the firstchannel layer 322 in FIG. 4E.

Hereinafter, as an example, a write operation and a read operation forthe memory cell structure including the fourth gate electrode layerpattern 122 d, the first ferroelectric layer 312, the eighth portion322-h of the first channel layer 322 illustrated in FIGS. 4B to 4Ecorresponding to the fourth memory cell MC4 of the nonvolatile memorydevice illustrated in FIG. 4A will be described. Substantially the samewrite and read operations may be applied to the memory cell structuresof FIGS. 4B to 4E corresponding to the first to third memory cells MC1,MC2 and MC3.

The write operation for the fourth memory cell MC4 may be describedusing FIGS. 4B to 4D. Referring to FIG. 4B, the fourth gate electrodelayer pattern 122 d is selected from the first to fourth gate electrodelayer patterns 122 a, 122 b, 122 c and 122 d of the first gate structure12. Subsequently, the source electrode structure 22 and the drainelectrode structure 24 are grounded, and a first polarization switchingvoltage having a positive polarity is applied to the fourth gateelectrode layer pattern 122 d. The first polarization switching voltagemay be a voltage having an absolute value equal to or greater than apredetermined threshold voltage, such that the polarization orientationof the first ferroelectric layer 312 can be switched. When the firstpolarization switching voltage is applied, as illustrated in FIG. 4C, afirst polarization DP1 may be formed in a region of the firstferroelectric layer 312 covered by or common to the fourth gateelectrode layer pattern 122 d. The first polarization DP1 may beoriented from an interface region of the first ferroelectric layer 312contacting the fourth gate electrode layer pattern 122 d towards aninterface region of the first ferroelectric layer 312 contacting thefirst channel layer 322. Subsequently, the first polarization switchingvoltage is removed. Even after the first polarization switching voltageis removed, the first polarization DP1 may be stored in the form ofremanent polarization. In addition, the first polarization DP1 isformed, so that positive charges CP and negative charges CN may begenerated in the inner region of the first ferroelectric layer 312. Evenafter the first polarization switching voltage is removed, the positivecharges CP may be distributed in the interface region of the firstferroelectric layer 312 in contact with the first channel layer 322, andthe negative charges CN may be distributed in the interface region ofthe first ferroelectric layer 312 in contact with the fourth gateelectrode layer pattern 122 d.

As another embodiment, in FIG. 4B, the fourth gate electrode layerpattern 122 d is selected from the first to fourth gate electrode layerpatterns 122 a, 122 b, 122 c and 122 d. Subsequently, after the sourceelectrode structure 22 and the drain electrode structure 24 aregrounded, a second polarization switching voltage having a negativepolarity is applied to the fourth gate electrode layer pattern 122 d.The second polarization switching voltage may be a voltage having anabsolute value equal to or greater than a predetermined thresholdvoltage to switch the polarization orientation of the firstferroelectric layer 312. When the second polarization switching voltageis applied, as described in FIG. 4D, a second polarization DP2 may beformed in an inner region of the first ferroelectric layer 312 coveredby the fourth gate electrode layer pattern 122 d. The secondpolarization DP2 may be oriented from the interface region of the firstferroelectric layer 312 contacting the first channel layer 322 towardsthe interface region of the first ferroelectric layer 312 contacting thefourth gate electrode layer pattern 122 d. Subsequently, the secondpolarization switching voltage is removed. Even after the secondpolarization switching voltage is removed, the second polarization DP2may be stored in the form of remanent polarization. In addition, thesecond polarization DP2 is formed, so that positive charges CP andnegative charges CN may be generated in the inner region of the firstferroelectric layer 312. Even after the second polarization switchingvoltage is removed, the positive charges CP may be distributed in theinterface region of the first ferroelectric layer 312 contacting thefourth gate electrode layer pattern 122 d, and the negative charges CNmay be distributed in the interface region of the first ferroelectriclayer 312 contacting the first channel layer 322. As described above,the write operation can be performed through the switching operation ofthe polarization orientation of the first ferroelectric layer 312described above with reference to FIGS. 4B to 4D. As an example, thefirst polarization DP1 forming operation related to FIG. 4C may bereferred to as a program operation, and the second polarization DP2forming operation related to FIG. 4D may be referred to as an eraseprogram.

Meanwhile, a read operation on the signal information stored in thefourth memory cell MC4 will be described with reference to FIGS. 4B and4E. First, a read voltage having an absolute value equal to or greaterthan a predetermined threshold voltage is applied to the fourth gateelectrode layer pattern 122 d. The absolute value of the read voltagemay be smaller than the absolute value of the first and secondpolarization switching voltages. That is, the polarization of the firstferroelectric layer 312 covered by the fourth gate electrode layerpattern 122 d may not be switched by the read voltage.

Instead, a conductive channel CH4 may be formed in the eighth region322-h of the first channel layer 322 adjacent to the first ferroelectriclayer 312 by the read voltage. Referring to FIG. 4E, the conductivechannel CH4 may electrically connect the source electrode structure 22to the drain electrode structure 24. The electron density inside theconductive channel CH4 may be higher than the electron density of thefirst channel layer 322 outside the conductive channel CH4.

After the conductive channel CH4 is formed, a source-drain potentialdifference is formed between the source electrode structure 22 and thedrain electrode structure 24. As an example, after the source electrodestructure 22 is grounded, a drain voltage having a positive polarity maybe applied to the drain electrode structure 24. Accordingly, electronsmay flow from the source electrode structure 22 to the drain electrodestructure 24 through the conductive channel CH4. At this time, thecurrent density generated by the flow of the electrons may be influencedby the orientation of the remanent polarization stored in the adjacentfirst ferroelectric layer 312. When the orientation of the remanentpolarization is the same as that of the first polarization DP1 of FIG.4C, the electron density inside the conductive channel CH4 increases, sothat the current density flowing along the conductive channel CH4 mayincrease. Conversely, when the orientation of the remanent polarizationis the same as that of the second polarization DP2 in FIG. 4D, theelectron density inside the conductive channel CH4 decreases, so thatthe current density flowing along the conductive channel CH4 maydecrease. As described above, by forming a conductive channel in achannel layer of a memory cell to be read, and by measuring the currentflowing through the conductive channel, the signal stored in the memorycell can be read.

According to an embodiment of the present disclosure, a nonvolatilememory device may include a gate structure, a source electrode structureand a drain electrode structure disposed in a direction perpendicular toa substrate. In addition, the nonvolatile memory device may include aferroelectric layer and a channel layer disposed adjacent to the gatestructure, the source electrode structure and the drain electrodestructure. In the nonvolatile memory device, a plurality of memory cellsmay be randomly accessed through independently selectable gate electrodelayer patterns. Through this, the nonvolatile memory device canindependently perform write and read operations on the accessed memorycell.

FIG. 5 is a perspective view schematically illustrating a nonvolatilememory device 2 according to another embodiment of the presentdisclosure. FIG. 6A is a circuit diagram schematically illustrating thenonvolatile memory device of FIG. 5. FIG. 6B is a partial plan view ofthe nonvolatile memory device, corresponding to the circuit diagram ofFIG. 6A, and FIG. 6C is a cross-sectional view taken along a line C-C′of FIG. 6B. FIGS. 6A and 6B may be views schematically illustrating oneoperation unit 2 a of the nonvolatile memory device 2 of FIG. 5.

Referring to FIG. 5, the nonvolatile memory device 2 may include aplurality of source electrode structures 22 a and 22 b, a plurality ofdrain electrode structures 24 a and 24 b, and insulation structures 26a, 26 b and 27 disposed on a base insulation layer 110 along a seconddirection (i.e., the y-direction), as compared to the nonvolatile memorydevice 1 described above with reference to FIGS. 1 to 3. As anembodiment, as illustrated, a first source electrode structure 22 a, afirst insulation structure 26 a, a first drain electrode structure 24 a,an inter-element insulation structure 27, a second source electrodestructure 22 b, a second insulation structure 26 b, and a second drainelectrode structure 24 b may be sequentially disposed along the seconddirection (i.e., the y-direction). Although the numbers of the sourceelectrode structures, the drain electrode structures, and the insulationstructures are shown as two in FIG. 5, devices contemplated by thedisclosure are not necessarily limited thereto. In other embodiments,the numbers of the source electrode structures, the drain electrodestructures, and the insulation structures may vary along the seconddirection (i.e., the y-direction).

Meanwhile, referring to FIG. 5, the first and second gate structures 12and 14, the first and second ferroelectric layers 312 and 314, and thefirst and second channel layers 322 and 324 may extend along the seconddirection (i.e., the y-direction) on the base insulation layer 110, andcover the plurality of source electrode structures 22 a and 22 b, theplurality of drain electrode structures 24 a and 24 b, and theinsulation structures 26 a, 26 b and 27. A first operation unit 2 aillustrated in FIGS. 6B and 6C may correspond to a portion of thenonvolatile memory device 2 of FIG. 5. As an example, the firstoperation unit 2 a may include the first gate structure 12, the firstferroelectric layer 312, the first channel layer 322, the first andsecond source electrode structures 22 a and 22 b, the first and seconddrain electrode structures 24 a and 24 b, and the insulation structures26 a, 26 b and 27. Referring to FIG. 5, a second operation unit 2 b maycorrespond to another portion of the nonvolatile memory device 2. As anexample, the second operation unit 2 b may include the second gatestructure 14, the second ferroelectric layer 314, the second channellayer 324, the first and second source electrode structures 22 a and 22b, the first and second drain electrode structures 24 a and 24 b, andthe insulation structures 26 a, 26 b and 27. Hereinafter, a method ofoperating the nonvolatile memory device 2 will be described using thefirst operation unit 2 a as an example, but the method may besubstantially equally applied to second operation unit 2 b, as well asto operation units in other embodiments.

Referring to FIGS. 5, 6A to 6C, a first global source line GSL1 and afirst global drain line GDL1 of FIG. 6A may correspond to the firstsource electrode structure 22 a and the first drain electrode structure24 a, respectively, of the first operation unit 2 a illustrated in FIGS.5, 6B and 6C. A second global source line GSL2 and a second global drainline GDL2 of FIG. 6A may correspond to the second source electrodestructure 22 b and the second drain electrode structure 24 b,respectively, of the first operation unit 2 a illustrated in FIGS. 5, 6Band 6C. A first global gate line GGL1 of FIG. 6A may correspond to thefirst gate electrode layer pattern 122 a of the first operation unit 2 aillustrated in FIGS. 5, 6B and 6C. Likewise, second to fourth globalgate lines GGL2, GGL3 and GGL4 of FIG. 6A may correspond to the secondto fourth gate electrode layer patterns 122 b, 122 c and 122 d,respectively, of the first operation unit 2 a illustrated in FIGS. 5, 6Band 6C.

Referring to FIG. 6A, the first to fourth memory cells MC1, MC2, MC3 andMC4 may each be connected to the first global source line GSL1 and thefirst global drain line GDL1. Likewise, the fifth to eighth memory cellsMC5, MC6, MC7 and MC8 may each be connected to the second global sourceline GSL2 and the second global drain line GDL2. The first and fifthmemory cells MC1 and MC5 may be connected to the first global gate lineGGL1 and may have first and fifth ferroelectric layers FD1 and FDS,respectively. Likewise, the second and sixth memory cells MC2 and MC6may be connected to the second global gate line GGL2 and may have secondand sixth ferroelectric layers FD2 and FD6, respectively. The third andseventh memory cell MC3 and MC7 may be connected to a third global gateline GGL3 and may have third and seventh ferroelectric layers FD3 andFD7, respectively. The fourth and eighth memory cells MC4 and MC8 may beconnected to a fourth global gate line GGL4 and may have fourth andeighth ferroelectric layers FD4 and FD8, respectively.

Hereinafter, as examples of an embodiment, a write operation and a readoperation will be described for a memory cell structure including thefourth gate electrode layer pattern 122 d, the first ferroelectric layer312, and the eighth portion 322 a-8 of the first channel part 322 a ofthe first operation unit 2 a shown in FIGS. 5, 6B and 6C. Thesestructures correspond to components of the fourth memory cell MC4 of thenonvolatile memory device illustrated in FIG. 6A. Similarly,substantially same write operation and read operation may be performedwith structures corresponding to the first to third and fifth to eighthmemory cells MC1, MC2, MC3, MC5, MC6, MC7 and MC8.

Referring to FIG. 6C, the first channel layer 322 may include, along thesecond direction (i.e., the y-direction), a first channel part 322 adisposed between the first source electrode structure 22 a and the firstdrain electrode structure 24 a, a second channel part 322 b disposedbetween the second source electrode structure 22 b and the second drainelectrode structure 24 b, and a third channel part 322 c disposedbetween the first drain electrode structure 24 a and the second sourceelectrode structure 22 b. The first to third channel parts 322 a, 322 band 322 c may include second portions 322 a-2, 322 b-2 and 322 c-2overlapping the first gate electrode layer pattern 122 a; fourthportions 322 a-4, 322 b-4 and 322 c-4 overlapping the second gateelectrode layer pattern 122 b; sixth portions 322 a-6, 322 b-6 and 322c-6 overlapping the third gate electrode layer pattern 122 c; and eighthportions 322 a-8, 322 b-8 and 322 c-8 overlapping the fourth gateelectrode layer pattern 122 d. Similarly, the first to third channelparts 322 a, 322 b and 322 c may include first portions 322 a-1, 322 b-1and 322 c-1 overlapping the first gate insulation layer pattern 132 a;third portions 322 a-3, 322 b-3 and 322 c-3 overlapping the second gateinsulation layer pattern 132 b; fifth portions 322 a-5, 322 b-5 and 322c-5 overlapping the third gate insulation layer pattern 132 c; andseventh portions 322 a-7, 322 b-7 and 322 c-7 overlapping the fourthgate insulation layer pattern 132 d; and ninth portions 322 a-9, 322 b-9and 322 c-9 overlapping the fifth gate insulation layer pattern 132 e.

Meanwhile, in relation to a write operation for the fourth memory cellMC4 in FIG. 6A, the fourth global word line GGL4 is selected from thefirst to fourth global word lines GGL1, GGL2, GGL3 and GGL4. Apolarization switching voltage Vs having a magnitude equal to or greaterthan a predetermined threshold voltage may be applied to the fourthglobal word line GGL4, and the polarization switching voltage Vs may beapplied to gate electrodes of the fourth memory cell MC4 and the eighthmemory cell MC8. The polarization switching voltage Vs is a voltagecapable of switching the polarization of the fourth ferroelectric layerFD4 of the fourth memory cell MC4 and the eighth ferroelectric layer FD8of the eighth memory cell MC8. However, in order to perform the writeoperation only on the fourth memory cell MC4, the first global sourceline GSL1 and the first global drain line GDL1 may be grounded, and apredetermined voltage Vp having an absolute value smaller than anabsolute value of the polarization switching voltage Vs may beseparately applied to the second global source line GSL2 and the secondglobal drain line GDL2. In this manner, the polarization switchingvoltage Vs is only applied to the fourth ferroelectric layer FD4 of thefourth memory cell MC4, and a voltage corresponding to a differencebetween the polarization switching voltage Vs and the predeterminedvoltage Vp may be applied to the eighth ferroelectric layer FD8 of theeighth memory cell MC8. Accordingly, when the polarization switchingvoltage Vs is applied to the global gate line GGL4, the polarization ofthe fourth ferroelectric layer FD4 of the fourth memory cell MC4 isswitched, and the polarization of the eighth ferroelectric layer FD8 ofthe eighth memory cell MC8 is not switched.

The write operation for storing the switched polarization in the form ofremanent polarization in the fourth ferroelectric layer FD4 issubstantially the same as the write operation of the first ferroelectriclayer 312 described above with reference to FIGS. 4A to 4D and will notbe repeated here, however through such a similar method, the writeoperation may be performed on the fourth memory cell MC4.

The above-described write operation for the fourth memory cell MC4 canalso be explained using the corresponding structures 2 and 2 a shown inFIGS. 5 and 6B. First, a polarization switching voltage Vs is applied tothe fourth gate electrode layer pattern 122 d corresponding to thefourth global word line GGL4. At this time, the first source electrodestructure 22 a and the first drain electrode structure 24 a respectivelycorresponding to the first global source line GSL1 and the first globaldrain line GDL1 may be grounded. On the other hand, a predeterminedvoltage Vp having a magnitude smaller than the polarization switchingvoltage Vs may be applied to the second source electrode structure 22 band the second drain electrode structure 24 b respectively correspondingto the second global source line GSL2 and the second global drain lineGDL2. By doing so, polarization within a first region of the firstferroelectric layer 312, positioned between the first source electrodestructure 22 a and the first drain electrode structure 24 a along thesecond direction, and in contact with the fourth gate electrode layerpattern 122 d, may be switched. Meanwhile, a voltage substantiallysmaller than the polarization switching voltage Vs is applied to asecond region of the first ferroelectric layer 312, positioned betweenthe second source electrode structure 22 b and the second drainelectrode structure 24 b along the second direction while in contactwith the fourth gate electrode layer pattern 122 d. Consequently, thepolarization in this second region of the first ferroelectric layer 312is not switched.

After the polarization switching voltage Vs is removed, the switchedpolarization may be stored in the form of remanent polarization. Thefirst region of the first ferroelectric layer 312 with the switchedpolarization may be a region overlapping the eighth portion 322 a-8 ofthe first channel part 322 a of FIG. 6C. The second region of the firstferroelectric layer 312 without a switched polarization may be a regionoverlapping the eighth portion 322 b-8 of the second channel part 322 bof FIG. 6C.

Meanwhile, a read operation for remanent polarization stored in thefourth memory cell MC4 will be explained. First, in FIG. 6A, the fourthglobal word line GGL4 is selected. Subsequently, a read voltage Vr equalto or greater than a predetermined threshold voltage may be applied tothe gate electrodes of the fourth memory cell MC4 and the eighth memorycell MC8 through the fourth global word line GGL4. An absolute value ofthe read voltage Vr may be smaller than an absolute value of thepolarization switching voltage Vs. That is, polarization inside thefourth ferroelectric layer FD4 and the eighth ferroelectric layer FD8may not be switched by the read voltage Vr. Transistors of the fourthmemory cell MC4 and the eighth memory cell MC8 are turned on by the readvoltage Vr, and conductive channels may be formed in the channel layersof the transistors. When a source-drain potential difference is formedbetween the first global source line GSL1 and the first global drainline GDL1, a source-drain current may flow only through the conductivechannel of the fourth memory cell MC4. The signal information of theremanent polarization stored in the fourth memory cell MC4 can be readby measuring the magnitude of the source-drain current because themagnitude of the source-drain current changes according to theorientation of the remanent polarization stored in the fourthferroelectric layer FD4 of the fourth memory cell MC4. On the otherhand, when a potential difference is not formed between the secondglobal source line GSL2 and the second global drain line GDL2, theoperation current may not flow through the conductive channel of theeighth memory cell MC8.

The above-described read operation for the fourth memory cell MC4 mayalso be explained in the same manner referring to FIGS. 5, 6B and 6C.First, the read voltage Vr is applied to the fourth gate electrode layerpattern 122 d corresponding to the fourth global word line GGL4. Aconductive channel CH100 may be formed in the channel layer 322overlapping the fourth gate electrode layer pattern 122 d by the readvoltage Vr. Subsequently, a source-drain voltage is applied between thefirst source electrode structure 22 a and the first drain electrodestructure 24 a respectively corresponding to the first global sourceline GSL1 and the first global drain line GDL1 to form a potentialdifference. The potential difference is not formed between the secondglobal source line GSL2 and the second global drain line GDL2. As aresult, a source-drain current may flow only through the conductivechannel CH100 between the first source electrode structure 22 a and thefirst drain electrode structure 24 a. The read operation for the fourthmemory cell MC4 may be performed by measuring the source-drain current.

Through the above-described methods, it is possible to perform a writeoperation and a read operation through random access to the memory cellsof the first operation unit 2 a of the nonvolatile memory device 2 ofFIGS. 5, 6B and 6C. The write operation and the read operation for thefirst operation unit 2 a of the nonvolatile memory device 2 of FIGS. 5,6B and 6C may be equally applied to the second operation unit 2 b of thenonvolatile memory device 2.

FIG. 7 is a perspective view schematically illustrating a nonvolatilememory device 3 according to another embodiment of the presentdisclosure. FIG. 8 is a plan view of the nonvolatile memory device ofFIG. 7. FIG. 9 is a cross-sectional view taken along a line D-D′ of thenonvolatile memory device of FIG. 7.

Referring to FIGS. 7 to 9, a nonvolatile memory device 3 may furtherinclude first and second interfacial insulation layers 332 and 334, ascompared to the nonvolatile memory device 1 of FIGS. 1 to 3.

The first interfacial insulation layer 332 may be disposed between afirst ferroelectric layer 312 and a first channel layer 322. One surfaceof the first interfacial insulation layer 322 may contact a firstferroelectric layer 312 and another surface of the first interfacialinsulation layer 332 may contact the first channel layer 322. In anembodiment, the first interfacial insulation layer 332 may be disposedon a plane formed substantially parallel to the first and seconddirections (i.e., a y-z plane parallel to the z-direction andy-direction). The first interfacial insulation layer 332 may have apredetermined thickness t3 along a third direction (i.e., thex-direction). In an embodiment, the thickness t3 of the firstinterfacial insulation layer 332 may be smaller than the thickness t1 ofthe first ferroelectric layer 312.

The first interfacial insulation layer 332 can prevent the firstferroelectric layer from directly contacting the first channel layer322. That is, the first interfacial insulation layer 332 can preventdefect sites such as oxygen vacancies from being generated at aninterface between the first ferroelectric layer 312 and the firstchannel layer 322. The first interfacial insulation layer 332 may havean amorphous structure. The first interfacial insulation layer 332 mayhave a lower dielectric constant than the first ferroelectric layer 312.The first interfacial insulation layer 332 may be non-ferroelectric. Thefirst interfacial insulation layer 332 may, for example, include siliconoxide, silicon nitride, silicon oxynitride, aluminum oxide, and thelike.

The second interfacial insulation layer 334 may be disposed between asecond ferroelectric layer 314 and a second channel layer 324. Onesurface of the second interfacial insulation layer 334 may contact thesecond ferroelectric layer 314 and another surface of the secondinterfacial insulation layer 334 may contact the second channel layer324. The second interfacial insulation layer 334 can prevent the secondferroelectric layer 314 from directly contacting the second channellayer 324.

The second interfacial insulation layer 334 may have substantially thesame configuration as the first interfacial insulation layer 332. Thesecond interfacial insulation layer 334 may have a predeterminedthickness t3 along a third direction (i.e., the x-direction).

FIG. 10 is a perspective view schematically illustrating a nonvolatilememory device 4 according to yet another embodiment of the presentdisclosure. FIG. 11 is a plan view of the nonvolatile memory device ofFIG. 10. FIG. 12 is a cross-sectional view taken along the line E-E′ ofthe nonvolatile memory device of FIG. 10.

Referring to FIGS. 10 to 12, the nonvolatile memory device 4 may furtherinclude first and second floating electrode layers 342 and 344, ascompared to the nonvolatile memory device 3 of FIGS. 7 to 9. The firstand second floating electrode layers 342 and 344 may be formed of aconductive material.

The first floating electrode layer 342 may be disposed between aferroelectric layer 312 and a first interfacial insulation layer 332.One surface of the first floating electrode layer 342 may contact thefirst ferroelectric layer 312 and another surface of the first floatingelectrode layer 342 may contact the first interfacial insulation layer332. In an embodiment, the first floating electrode layer 342 may bedisposed on a plane defined by first and second directions (i.e., thez-direction and y-direction). The first floating electrode layer 342 mayhave a predetermined thickness t4 along a third direction (i.e., thex-direction).

The first floating electrode layer 342 may maintain an electricalfloating state. As an example, the first floating electrode layer 342 isnot electrically connected to first to fourth gate electrode layerpatterns 122 a, 122 b, 122 c and 122 d and a first channel layer 322 ofa first gate structure 12. The first floating electrode layer 342 maycharge positive charges or negative charges therein according to thepolarity of the voltage applied to the first to fourth gate electrodelayer patterns 122 a, 122 b, 122 c and 122 d. The charged positivecharges or negative charges may function to stabilize the remanentpolarization stored in the first ferroelectric layer 312. Thus, thepresence of the floating electrode layer improves the endurance andstability of the remanent polarization of the nonvolatile memory device4.

In addition, in an embodiment, a structure of a nonvolatile memorydevice includes the first ferroelectric layer 312, having a relativelyhigh dielectric constant, which is electrically connected in series tothe first interfacial insulation layer 332 having a relatively lowdielectric constant. When the polarization switching voltage or the readvoltage is applied to the series connection structure, if the firstfloating electrode layer 342 is not present, a relatively high voltagemay be applied to the first interfacial insulation layer 332 having arelatively low dielectric constant. Due to the thinness of the firstferroelectric layer 312 and the first interfacial insulation layer 332,the first interfacial insulation layer 332 may be in effect electricallydestroyed. Conversely, when the first floating electrode layer 342 isinterposed between the first ferroelectric layer 312 and the firstinterfacial insulation layer 332, the first floating electrode layer 342can suppress the application of a relatively high voltage to the firstinterfacial insulation layer 332 thereby improving the endurance andreliability of the nonvolatile memory device 4.

Likewise, the second floating electrode layer 344 may be disposedbetween the second ferroelectric layer 314 and the second interfacialinsulation layer 334. As an example, the second floating electrode layer344 is not electrically connected to the first to fourth gate electrodelayer patterns 124 a, 124 b, 124 c and 124 d of the second gatestructure 14 and the second channel layer 324. One surface of the secondfloating electrode layer 344 may contact the second ferroelectric layer314 and another surface of the second floating electrode layer 344 maycontact the second interfacial insulation layer 334. In an embodiment,the second floating electrode layer 344 may be disposed on a planeformed substantially parallel to the first and second directions (i.e.,a y-z plane parallel to the z-direction and y-direction). The secondfloating electrode layer 344 may have a predetermined thickness t4 alongthe third direction (i.e., the x-direction). The configuration andfunction of the second floating electrode layer 344 may be substantiallythe same as the configuration and function of the first floatingelectrode layer 342. That is, the second floating electrode layer 344can improve the retention of the remanent polarization stored in thesecond ferroelectric layer 314 and the endurance of the secondinterfacial insulation layer 334.

FIG. 13 is a perspective view schematically illustrating a nonvolatilememory device 5 according to still yet another embodiment of the presentdisclosure. FIG. 14 is a plan view of the nonvolatile memory device ofFIG. 13. FIG. 15 is a cross-sectional view taken along a line F-F′ ofthe nonvolatile memory device of FIG. 13.

Referring to FIGS. 13 to 15, the nonvolatile memory device 5 may furtherinclude third and fourth interfacial insulation layers 352 and 354, ascompared to the nonvolatile memory device 3 of FIGS. 7 to 9.

The third interfacial insulation layer 352 may be disposed between afirst gate structure 12 and a first ferroelectric layer 312. As anexample, one surface of the third interfacial insulation layer 352 maycontact the first gate structure 12 and another surface of the thirdinterfacial insulation layer 352 may contact the first ferroelectriclayer 312. In an embodiment, the third interfacial insulation layer 352may be disposed on a plane formed substantially parallel to the firstand second directions (i.e., a y-z plane parallel to the z-direction andy-direction). The third interfacial insulation layer 352 may have apredetermined thickness t5 along the third direction (i.e., thex-direction). In an embodiment, the thickness t5 of the thirdinterfacial insulation layer 352 may be smaller than the thickness t1 ofthe first ferroelectric layer 312.

The third interfacial insulation layer 352 can prevent the firstferroelectric layer 312 from directly contacting the first gatestructure 12. The third interfacial insulation layer 352 can preventdefect sites from being generated at interfaces between the firstferroelectric layer 312 and the first to fourth gate electrode layerpatterns 122 a, 122 b, 122 c and 122 d of the first gate structure 12.The third interfacial insulation layer 352 may have an amorphousstructure. The third interfacial insulation layer 352 may have a lowerdielectric constant than the first ferroelectric layer 312. The thirdinterfacial insulation layer 352 may be non-ferroelectric. As anexample, the third interfacial insulation layer 352 may have aparaelectric property. The third interfacial insulation layer 352 may,for example, include silicon oxide, silicon nitride, silicon oxynitride,aluminum oxide, and the like.

The third interfacial insulation layer 352 may be formed ofsubstantially the same material as the first interfacial insulationlayer 332. The thickness t5 of the third interfacial insulation layer352 may be substantially the same as the thickness t3 of the firstinterfacial insulation layer 332.

Likewise, the fourth interfacial insulation layer 354 may be disposedbetween the second gate structure 14 and the second ferroelectric layer314. As an example, one surface of the fourth interfacial insulationlayer 354 may contact the second gate structure 14 and another surfaceof the fourth interfacial insulation layer 354 may contact the secondferroelectric layer 314. In an embodiment, the fourth interfacialinsulation layer 354 may be disposed on a plane formed substantiallyparallel to the first and second directions (i.e., a y-z plane parallelto the z-direction and y-direction). The fourth interfacial insulationlayer 354 may have a thickness t5 along the third direction (i.e., thex-direction). In an embodiment, the thickness t5 of the fourthinterfacial insulation layer 354 may be smaller than the thickness t1 ofthe second ferroelectric layer 314.

The fourth interfacial insulation layer 354 can prevent the secondferroelectric layer 314 from directly contacting the second gatestructure 14. The fourth interfacial insulation layer 354 can preventdefect sites from being generated at interfaces between the secondferroelectric layer 314 and the first to fourth gate electrode patterns124 a, 124 b, 124 c and 124 d of the second gate structure 14. Thefourth interfacial insulation layer 354 may have an amorphous structure.The fourth interfacial insulation layer 354 may have a lower dielectricconstant than the second ferroelectric layer 314. The fourth interfacialinsulation layer 354 may be non-ferroelectric. As an example, the fourthinterfacial insulation layer 354 may have a paraelectric property. Thefourth interfacial insulation layer 354 may, for example, includesilicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, andthe like.

The fourth interfacial insulation layer 354 may be formed ofsubstantially the same material as the second interfacial insulationlayer 334. The thickness t5 of the fourth interfacial insulation layer354 may be substantially the same as the thickness t3 of the secondinterfacial insulation layer 334.

FIG. 16 is a perspective view schematically illustrating a nonvolatilememory device 6 according to still yet another embodiment of the presentdisclosure. FIG. 17 is a plan view of the nonvolatile memory device ofFIG. 16. FIG. 18 is a cross-sectional view taken along a line G-G′ ofthe nonvolatile memory device of FIG. 16.

Referring to FIGS. 16 to 18, the nonvolatile memory device 6 may bedifferentiated, as compared to the nonvolatile memory device 3 of FIGS.7 to 9, by configurations of first and second gate structures 1012 and1014.

In this embodiment, the first gate structure 1012 may include first tofourth gate electrode layer patterns 1122 a, 1122 b, 1122 c and 1122 dand first to fifth gate insulation layer patterns 1132 a, 1132 b, 1132c, 1132 d and 1132 e, which are alternately stacked along a firstdirection (i.e., the z-direction). The second gate structure 1014 mayinclude first to fourth gate electrode layer patterns 1124 a, 1124 b,1124 c and 1124 d and first to fifth gate insulation layer patterns 1134a, 1134 b, 1134 c, 1134 d and 1134 e, which are alternately stackedalong the first direction (i.e., the z-direction).

Referring to FIGS. 16 and 18, the first to fifth gate insulation layerpatterns 1132 a, 1132 b, 1132 c, 1132 d and 1132 e of the first gatestructure 1012 may separate a first ferroelectric layer 1312, a firstinterfacial insulation layer 1332 and a first channel layer 1322 withrespect to the second and third direction (i.e., the y-direction andx-direction). Accordingly, the first ferroelectric layer 1312, the firstinterfacial insulation layer 1332 and the first channel layer 1322 maybe discontinuously disposed in the first direction. In comparison withan embodiment described above with reference to FIGS. 7 to 9, the firstferroelectric layer 1312 of this embodiment may be disposed to contactportions of one sidewall surface of the first gate structure 1012, thatis, only sidewall surfaces of the first to fourth gate electrode layerpatterns 1122 a, 1122 b, 1122 c and 1122 d, in a lateral direction(i.e., the x-direction). In other words, the first ferroelectric layer1312 does not contact the first to fifth gate insulation layer patterns1132 a, 1132 b, 1132 c, 1132 d and 1132 e in the lateral direction(i.e., the x-direction). In addition, the first interfacial insulatinglayer 1332 and the first channel layer 1322 may be sequentially arrangedin a lateral direction from the first ferroelectric layer 1312, andbetween the first to fifth gate insulation layer patterns 1132 a, 1132b, 1132 c, 1132 d and 1132 e.

Referring to FIGS. 16 and 18, in comparison with the first to fifth gateinsulation layer patterns 132 a, 132 b, 132 c, 132 d and 132 e of anembodiment described above with reference to FIGS. 7 to 9, the first tofifth gate insulation layer patterns 1132 a, 1132 b, 1132 c, 1132 d and1132 e may be disposed to directly contact a source electrode structure22, a drain electrode structure 24 and an insulation structure 26. Inthis embodiment, the first to fifth gate insulation layer patterns 1132a, 1132 b, 1132 c, 1132 d and 1132 e can more effectively implementelectrical insulation between the first to fourth gate electrode layerpatterns 1122 a, 1122 b, 1122 c and 1122 d in the first direction (i.e.,the z-direction).

Likewise, referring to FIGS. 16 and 18, the first to fifth gateinsulation layer patterns 1134 a, 1134 b, 1134 c, 1134 d and 1134 e ofthe second gate structure 1014 can separate a second ferroelectric layer1314, a second interfacial insulation layer 1334, and a second channellayer 1324 from each other with respect to the second and thirddirection (i.e., the y-direction and x-direction). Accordingly, thesecond ferroelectric layer 1314, the second interfacial insulation layer1334, and the second channel layer 1324 may be discontinuously disposedin the first direction (i.e., the z-direction). Accordingly, incomparison with an embodiment described above with reference to FIGS. 7to 9, the second ferroelectric layer 1314 of this embodiment may bedisposed to contact portions of one sidewall surface of the second gatestructure 1014, that is, only sidewall surfaces of the first to fourthgate electrode layer patterns 1124 a, 1124 b, 1124 c and 1124 d, in alateral direction (i.e., the x-direction). In other words, the secondferroelectric layer 1314 does not contact the first to fifth gateinsulation layer patterns 1134 a, 1134 b, 1134 c, 1134 d and 1134 e inthe lateral direction (i.e., the x-direction).

Referring to FIGS. 16 and 18, in comparison with the first to fifth gateinsulation layer patterns 134 a, 134 b, 134 c, 134 d and 134 e of anembodiment described above with reference to FIGS. 7 to 9, the first tofifth gate insulation layer patterns 1134 a, 1134 b, 1134 c, 1134 d and1134 e may be disposed to directly contact the source electrodestructure 22, the drain electrode structure 24 and the insulationstructure 26. In this embodiment, the first to fifth gate insulationlayer patterns 1134 a, 1134 b, 1134 c, 1134 d and 1134 e can moreeffectively implement electrical insulation between the first to fourthgate electrode layer patterns 1124 a, 1124 b, 1124 c and 1124 d in thefirst direction (i.e., the z-direction).

Meanwhile, the material properties and functions of the first to fourthgate electrode layer patterns 1122 a, 1122 b, 1122 c, 1122 d, 1124 a,1124 b, 1124 c and 1124 d of the first and second gate structures 1012and 1014, the first and second ferroelectric layers 1312 and 1314, thefirst and second interfacial insulation layers 1332 and 1334, the firstand second channel layers 1322 and 1324, and the first to fifth gateinsulation layer patterns 1132 a, 1132 b, 1132 c, 1132 d, 1132 e, 1134a, 1134 b, 1134 c, 1134 d and 1134 e are substantially the same as thematerial properties and functions of the first to fourth gate electrodelayer patterns 122 a, 122 b, 122 c, 122 d, 124 a, 124 b, 124 c and 124 dof the first and second gate structures 12 and 14, the first and secondferroelectric layers 312 and 314, the first and second interfacialinsulation layers 332 and 334, the first and second channel layers 322and 324, and the first to fifth gate insulation layer patterns 132 a,132 b, 132 c, 132 d, 1132 e, 134 a, 134 b, 1134 c, 134 d and 134 e,respectively.

FIG. 19 is a perspective view schematically illustrating a nonvolatilememory device 7 according to a further embodiment of the presentdisclosure. FIG. 20 is a plan view of the nonvolatile memory device ofFIG. 19. FIG. 21 is a cross-sectional view taken along a line H-H′ ofthe nonvolatile memory device of FIG. 19.

Referring to FIGS. 19 to 21, a nonvolatile memory device 7 may bedifferentiated, as compared to the nonvolatile memory device 4 of FIGS.10 to 12, by configurations of first and second ferroelectric layerparts 2312 and 2314, first and second floating electrode layer parts2342 and 2344, and first and second gate structures 2012 and 2014.

The first gate structure 2012 may include first to fourth gatefunctional layer patterns 2112 a, 2112 b, 2112 c and 2112 d and first tofifth gate insulation layer patterns 2132 a, 2132 b, 2132 c, 2132 d and2132 e, which are alternately stacked along a first direction (i.e., thez-direction) on the base insulation layer 110. The first gate structure2012 may extend in a second direction (i.e., the y-direction).

A first interfacial insulation layer 332 may be disposed on one sidewallsurface S7 of the first gate structure 2012. That is, the firstinterfacial insulation layer 332 may be disposed to cover the onesidewall surface S7 of the first gate structure 2012. The one sidewallsurface S7 is a plane formed substantially parallel to the first andsecond directions (i.e., a y-z plane parallel to the z-direction andy-direction). In a specific embodiment, the first interfacial insulationlayer 332 may be disposed to contact the first to fifth gate insulationlayer patterns 2132 a, 2132 b, 2132 c, 2132 d and 2132 e and the firstfloating electrode layer part 2342.

In addition, the first channel layer 322 may be disposed to contact thefirst interfacial insulation layer 332. The first channel layer 322 maybe disposed on a plane formed substantially parallel to the first andsecond directions (i.e., a y-z plane parallel to the z-direction andy-direction).

Referring to FIG. 21, the first to fourth gate functional layer patterns2112 a, 2112 b, 2112 c and 2112 d of the first gate structure 2012 mayeach have a first floating electrode layer part 2342, a firstferroelectric layer part 2312, and a first gate electrode layer part2122. As an example, in the first gate functional layer pattern 2112 a,the first floating electrode layer part 2342 may be disposed on thefirst interfacial insulation layer 332, and the first and second gateinsulation layer patterns 2132 a and 2132 b. The first floatingelectrode layer part 2342 may have a predetermined thickness t6 in thex-direction from the first interfacial insulation layer 332, and in thez-direction from the first and second gate insulation layer patterns2132 a and 2132 b. The first ferroelectric layer part 2312 may bedisposed on the first floating electrode layer part 2342, and the firstand second gate insulation layer patterns 2132 a and 2132 b. The firstferroelectric layer part 2312 may have a predetermined thickness t7common to the first floating electrode layer part 2342. The first gateelectrode layer part 2122 may be disposed to contact or cover the firstferroelectric layer part 2312 between the first and second gateinsulation layer patterns 2132 a and 2132 b.

With respect to the second gate functional layer pattern 2112 b, thefirst floating electrode layer part 2342, the first ferroelectric layerpart 2312, and the first gate electrode layer part 2122 may be disposedbetween second and third gate insulation layer patterns 2132 b and 2312c and contact the first interfacial insulation layer 332 insubstantially the same manner. As another example, with the third gatefunctional layer pattern 2112 c, the first floating electrode layer part2342, the first ferroelectric layer part 2312, and the first gateelectrode layer part 2122 may be disposed between the third and fourthgate insulation layer patterns 2132 c and 2132 d and contact the firstinterfacial insulation layer 332 in substantially the same manner. Inthe case of the fourth gate functional layer pattern 2112 d, the firstfloating electrode layer part 2342, the first ferroelectric layer part2312, and the first gate electrode layer part 2122 may be disposedbetween the fourth and fifth gate insulation layer patterns 2132 d and2132 e and the contact first interfacial insulation layer 332 insubstantially the same manner.

Referring to FIGS. 19 to 21, a source electrode structure 22, a drainelectrode structure 24 and an insulation structure 26 may be disposed onthe base insulation layer 110 to contact a first channel layer 322. Inaddition, a second channel layer 324 may be disposed, on the baseinsulation layer 110 to contact one sidewall surface of each of thesource electrode structure 22, the drain electrode structure 24 and theinsulation structure 26. In addition, a second interfacial insulationlayer 334 may be disposed to contact the second channel layer 324.

On the base insulation layer 110, the second gate structure 2014 may bedisposed to contact the second interfacial insulation layer 334. Thesecond gate structure 2014 may include first to fourth gate functionallayer patterns 2114 a, 2114 b, 2114 c and 2114 d and first to fifth gateinsulation layer patterns 2134 a, 2134 b, 2134 c, 2134 d and 2134 e,which are alternately stacked on the base insulation layer 110 along thefirst direction (i.e., the z-direction). The second gate structure 2014may extend in the second direction (i.e., the y-direction).

The first to fourth gate functional layer patterns 2114 a, 2114 b, 2114c and 2114 d of the second gate structure 2014 may each have a secondfloating electrode layer part 2344, a second ferroelectric layer part2314 and a second gate electrode layer part 2124. The configurations ofthe second floating electrode layer part 2344, the second ferroelectriclayer part 2314 and the second gate electrode layer part 2124 of thesecond gate structure 2014 may be substantially the same as theconfigurations of the first floating electrode layer part 2342, thefirst ferroelectric layer part 2312, and the first gate electrode layerpart 2122 of the first gate structure 2012.

When comparing the nonvolatile memory device 7 according to theabove-described embodiment with the nonvolatile memory device 4 of FIGS.10 to 12, in the first to fourth gate functional layer patterns 2112 a,2112 b, 2112 c and 2112 d of first gate structure 2012 and the first tofourth gate functional layer patterns 2114 a, 2114 b, 2114 c and 2114 dof second gate structure 2014, the areas of the first and secondferroelectric layer parts 2312 and 2314 that respectively contact thefirst and second gate electrode layer parts 2122 and 2124 can beincreased. In addition, the areas of the first and second floatingelectrode layer parts 2342 and 2344 contacting the first and secondferroelectric layer parts 2312 and 2314 can be increased. As a result,by increasing the areas of the first and second ferroelectric layerparts 2312 and 2314 functioning as memory layers, the density of theremanent polarization stored in the ferroelectric layer parts 2313 and2314 can be increased. As a result, the reliability of the memoryoperation can be improved.

Meanwhile, the material properties and functions of the first and secondgate electrode layer parts 2122 and 2144, the first and secondferroelectric layer parts 2312 and 2314, the first and second floatingelectrode layer parts 2342 and 2344, the first to fifth gate insulationslayer patterns 2132 a, 2132 b, 2132 c, 2132 d, 2132 e, 2134 a, 2134 b,2134 c, 2134 d and 2134 e of the first and second gate structures 2012and 2014 are substantially the same as the material properties andfunctions of the first to fourth gate electrode layer patterns 122 a,122 b, 122 c, 122 d, 124 a, 124 b, 124 c and 124 d of the first andsecond gate structures 12 and 14, the first and second ferroelectriclayers 312 and 314, the first and second floating electrode layers 342and 344, and the first to fifth gate insulation layer patterns 132 a,132 b, 132 c, 132 d, 132 e, 134 a, 134 b, 134 c, 134 d and 134 e of thefirst and second gate structures 12 and 14, respectively, of embodimentsdescribed above with reference to FIGS. 10 to 12.

FIG. 22 is a perspective view schematically illustrating a nonvolatilememory device 8 according to a still further embodiment of the presentdisclosure. FIG. 23 is a plan view of the nonvolatile memory device ofFIG. 22. FIG. 24 is a cross-sectional view taken along a line I-I′ ofthe nonvolatile memory device of FIG. 22.

Referring to FIGS. 22 to 24, a nonvolatile memory device 8 isdifferentiated, as compared to a nonvolatile memory device 1 of FIGS. 1to 3, in a configuration of a channel structure 28.

In this embodiment, a channel structure 28 replaces an insulationstructure 26 in the nonvolatile memory device 1 of FIGS. 1 to 3. Thatis, the channel structure 28 may be disposed to contact a sourceelectrode structure 22 and a drain electrode structure 24 in a seconddirection (i.e., the y-direction). Further, the channel structure 28 maybe disposed to contact first and second ferroelectric layers 312 and 314in a third direction (i.e., the x-direction). Accordingly, the first andsecond channel layers 322 and 324 of the nonvolatile memory device 1 ofFIGS. 1 to 3 are omitted from the nonvolatile memory device 8 of thisembodiment.

The channel structure 28 may have a pillar-like shape extending in afirst direction (i.e., the z-direction) from a base insulation layer110. When a read voltage is applied to at least one of first to fourthgate electrode layer patterns 122 a, 122 b, 122 c and 122 d of a firstgate structure 12, a conductive channel may be formed in a region of thechannel structure 28, overlapping the at least one gate electrode layerpattern. Likewise, when the read voltage is applied to at least one offirst to fourth gate electrode layer patterns 124 a, 124 b, 124 c and124 d of a second gate structure 14, a conductive channel may be formedin a region of the channel structure 28, overlapping the at least onegate electrode layer pattern.

The channel structure 28 may, for example, include a doped semiconductormaterial or metal oxide. The semiconductor material may, for example,include silicon (Si), germanium (Ge), gallium arsenide (GaAs), and thelike. The metal oxide may include indium-gallium-zinc (In-Ga—Zn) oxide.In an embodiment, the channel structure 28 may include silicon (Si)doped with an n-type dopant. Alternatively, the channel structure 28 mayinclude c-axis aligned indium-gallium-zinc (In-Ga—Zn) oxide. The channelstructure 28 may have a single crystal structure or a polycrystallinestructure.

As described above, the nonvolatile memory device 8 of the presentembodiment may include a pillar-shaped channel structure 28. The devicestructure and manufacturing process can be simplified by using thechannel structure 28, at the same location, instead of the insulatingstructure 26 of the nonvolatile memory device 1 of FIGS. 1 to 3.

In other embodiments, in a nonvolatile memory device 2 of FIG. 5, anonvolatile memory device in which the insulation structures 26 a and 26b are replaced with channel structures 28 of the present embodiment maybe implemented, while omitting the first and second channel layers 322and 324. Likewise, in a nonvolatile memory device 3 of FIGS. 7 to 9, anonvolatile memory device 4 of FIGS. 10 to 12, a nonvolatile memorydevice 5 of FIGS. 13 to 15, and a nonvolatile memory device 7 of FIGS.19 to 21, nonvolatile memory devices in which the insulating structures26 are replaced with channel structures 28 of the present embodiment canbe implemented. In such embodiments, the first and second channel layers322 and 324 may be omitted. In addition, in a nonvolatile memory device6 of FIGS. 16 to 18, a nonvolatile memory device in which an insulatingstructure 26 is replaced with a channel structure 28 of the presentembodiment may be implemented, while omitting the first and secondchannel layers 1322 and 1324 of the nonvolatile memory device 6 of FIGS.16 to 18.

The embodiments of the inventive concept have been disclosed above forillustrative purposes. Those of ordinary skill in the art willappreciate that various modifications, additions and substitutions arepossible, without departing from the scope and spirit of the inventiveconcept as disclosed in the accompanying claims.

What is claimed is:
 1. A nonvolatile memory device comprising: asubstrate having an upper surface; a gate structure disposed over thesubstrate, the gate structure comprising at least one gate electrodelayer pattern and at least one gate insulation layer pattern, which arealternately stacked along a first direction perpendicular to the uppersurface, wherein the gate structure extends in a second directionperpendicular to the first direction; a ferroelectric layer disposedover the substrate and disposed on at least a portion of one sidewallsurface of the gate structure, wherein the one sidewall surface of thegate structure forms a plane substantially parallel to the first andsecond directions; a channel layer disposed over the substrate anddisposed on the ferroelectric layer; a source electrode structure and adrain electrode structure, spaced apart from each other in the seconddirection, each disposed over the substrate and disposed to contact thechannel layer; and a conductive channel formed in the channel layer,wherein the conductive channel extends in the second direction toelectrically connect the source electrode structure and the drainelectrode structure over the substrate.
 2. The nonvolatile memory deviceof claim 1, further comprising a base insulation layer disposed on thesubstrate to contact the gate structure, the ferroelectric layer, thechannel layer, the source electrode structure, and the drain electrodestructure.
 3. The nonvolatile memory device of claim 1, wherein theferroelectric layer has a predetermined thickness in a third directionperpendicular to the first and second directions.
 4. The nonvolatilememory device of claim 1, wherein the channel layer comprises a dopedsemiconductor material or metal oxide.
 5. The nonvolatile memory deviceof claim 1, wherein each of the source electrode structure and the drainelectrode structure has a pillar shape extending in the first direction.6. The nonvolatile memory device of claim 1, further comprising aninsulation structure disposed between the source electrode structure andthe drain electrode structure.
 7. The nonvolatile memory device of claim1, wherein the gate insulation layer pattern separates the ferroelectriclayer and the channel layer with the second direction and a thirddirection that is perpendicular to the first and second direction. 8.The nonvolatile memory device of claim 7, wherein the gate electrodelayer pattern is disposed to contact the ferroelectric layer in thethird direction, and wherein the gate insulation layer pattern isdisposed to contact the source electrode structure and the drainelectrode structure in the third direction.
 9. A nonvolatile memorydevice comprising: a substrate having an upper surface; a gate structuredisposed over the substrate, the gate structure comprising at least onegate electrode layer pattern and at least one gate insulation layerpattern, which are alternately stacked along a first directionperpendicular to the upper surface, wherein the gate structure extendsin a second direction perpendicular to the first direction; aferroelectric layer disposed on at least a portion of one sidewallsurface of the gate structure, wherein the one sidewall surface of thegate structure forms a plane substantially parallel to the first andsecond directions; a source electrode structure and a drain electrodestructure spaced apart from each other in the second direction, eachdisposed over the substrate and each disposed on the ferroelectriclayer; a channel structure disposed over the substrate and disposedbetween the source electrode structure and the drain electrodestructure, and a conductive channel formed in some portions of thechannel structure, wherein the conductive channel extends in the seconddirection to electrically connect the source electrode structure and thedrain electrode structure over the substrate.
 10. The nonvolatile memorydevice of claim 9, further comprising a base insulation layer disposedon the substrate to contact the gate structure, the ferroelectric layer,the source electrode structure, the drain electrode structure, and thechannel structure in the first direction.
 11. The nonvolatile memorydevice of claim 9, wherein the channel structure has a pillar shapeextending along the first direction.
 12. The nonvolatile memory deviceof claim 9, wherein the channel structure contacts the source electrodestructure and the drain electrode structure in the second direction, andcontacts the ferroelectric layer in a third direction perpendicular tothe first and second directions.